NH3-annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability
Applied Physics Letters 80 巻 7 号
1252-1254 頁
2002-02-18 発行
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| ファイル情報(添付) | |
| タイトル ( eng ) |
NH3-annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability
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| 作成者 |
Khosru Quazi Deen Mohd
Yoshimoto Takashi
Kidera Toshirou
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| 収録物名 |
Applied Physics Letters
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| 巻 | 80 |
| 号 | 7 |
| 開始ページ | 1252 |
| 終了ページ | 1254 |
| 抄録 |
Extremely thin (equivalent oxide thickness, Teq = 1.2 nm) silicon-nitride high-k (er = 7.2) gate dielectrics have been formed at low temperatures (<550 °C) by an atomic-layer-deposition (ALD) technique with subsequent NH3 annealing at 550 °C. A remarkable reduction in leakage current, especially in the low dielectric voltage region, which will be the operating voltage for future technologies, has made it a highly potential gate dielectric for future ultralarge-scale integrated devices. Suppressed soft breakdown events are observed in ramped voltage stressing. This suppression is thought to be due to a strengthened structure of Si–N bonds and the smoothness and uniformity at the poly-Si/ALD-silicon-nitride interface.
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| 言語 |
英語
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| 資源タイプ | 学術雑誌論文 |
| 出版者 |
American Institute of Physics
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| 発行日 | 2002-02-18 |
| 権利情報 |
Copyright (c) 2002 American Institute of Physics.
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| 出版タイプ | Version of Record（出版社版。早期公開を含む） |
| アクセス権 | オープンアクセス |
| 収録物識別子 |
[ISSN] 0003-6951
[DOI] 10.1063/1.1447314
[NCID] AA00543431
[DOI] http://dx.doi.org/10.1063/1.1447314
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