Temperature Dependence of Threshold Voltage in Poly-Si/TiN Metal Gate Transistors

Poly-Si/TiN金属ゲートトランジスタの閾値電圧の温度依存性

Nishida Yukio

Electrical engineering [ 540 ]

eng

・Y. Nishida, K. Eikyu, A. Shimizu, T. Yamashita, H. Oda, Y. Inoue, and K. Shibahara; Temperature Coefficient of Threshold Voltage in High-k Metal Gate Transistors with Various TiN and Capping Layer Thicknesses; Japanese Journal of Applied Physics 49 (2010) 04DC03, pp.04DC03-1－5. (doi: 10.1143/JJAP.49.04DC03) references

・Y. Nishida and S. Yokoyama; Mechanisms of Temperature Dependence of Threshold Voltage in High-k/Metal Gate Transistors with Different TiN Thicknesses; International Journal of Electronics, 103(4) 629-647 (2016). (doi: 10.1080/00207217.2015.1036809) references

・Y. Nishida, T. Yamashita, S. Yamanari, M. Higashi, K. Shiga, N. Murata, M. Mizutani, M. Inoue, S. Sakashita, K. Mori, J. Yugami, T. Hayashi, A. Shimizu, H. Oda, T. Eimori, and O. Tsuchiya; Performance Enhancement in 45-nm Ni Fully-Silicided Gate/High-k CMIS using Substrate Ion Implantation; Digest of 2006 Symposium on VLSI (2006) pp.172-173. (doi: 10.1109/VLSIT.2006.1705272) references

・Y. Nishida, T. Kawahara, S. Sakashita, M. Mizutani, S. Yamanari, M. Higashi, N. Murata, M. Inoue, J. Yugami, S. Endo, T. Hayashi, T. Yamashita, H. Oda, and Y. Inoue; Advanced Poly-Si NMIS and Poly-Si/TiN PMIS Hybrid-Gate High-k CMIS using PVD/CVD-Stacked TiN and Local Strain Technique; Digest of 2007 Symposium on VLSI (2007) pp. 214-215. (doi: 10.1109/VLSIT.2007.4339697) references

[DOI] http://doi.org/10.1143/JJAP.49.04DC03 references

[DOI] http://doi.org/10.1080/00207217.2015.1036809 references

[DOI] http://doi.org/10.1109/VLSIT.2006.1705272 references

[DOI] http://doi.org/10.1109/VLSIT.2007.4339697 references

広島大学