Low-temperature formation of silicon nitride gate dielectrics by atomic-layer deposition
Applied Physics Letters Volume 79 Issue 5
Page 665-667
published_at 2001-07-30
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| File | |
| Title ( eng ) |
Low-temperature formation of silicon nitride gate dielectrics by atomic-layer deposition
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| Creator |
Yoshimoto Takashi
Kidera Toshirou
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| Source Title |
Applied Physics Letters
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| Volume | 79 |
| Issue | 5 |
| Start Page | 665 |
| End Page | 667 |
| Abstract |
Thin (equivalent oxide thickness Teq of 2.4 nm) silicon nitride layers were deposited on Si substrates by an atomic-layer-deposition (ALD) technique at low temperatures (<550°C). The interface state density at the ALD silicon nitride/Si-substrate interface was almost the same as that of the gate SiO2. No hysteresis was observed in the gate capacitance-gate voltage characteristics. The gate leakage current was the level comparable with that through SiO2 of the same Teq. The conduction mechanism of the leakage current was investigated and was found to be the direct tunneling. The ALD technique allows us to fabricate an extremely thin, very uniform silicon nitride layer with atomic-scale control for the near-future gate dielectrics.
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| Language |
eng
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| Resource Type | journal article |
| Publisher |
American Institute of Physics
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| Date of Issued | 2001-07-30 |
| Rights |
Copyright (c) 2001 American Institute of Physics.
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| Publish Type | Version of Record |
| Access Rights | open access |
| Source Identifier |
[ISSN] 0003-6951
[DOI] 10.1063/1.1388026
[NCID] AA00543431
[DOI] http://dx.doi.org/10.1063/1.1388026
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