Mechanism of dynamic bias temperature instability in p- and nMOSFETs: The effect of pulse waveform

IEEE Transactions on Electron Devices Volume 53 Issue 8 Page 1805-1814 published_at 2006-08
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Title ( eng )
Mechanism of dynamic bias temperature instability in p- and nMOSFETs: The effect of pulse waveform
Creator
Zhu Shiyang
Ohashi Takuo
Miyake Hideharu
Source Title
IEEE Transactions on Electron Devices
Volume 53
Issue 8
Start Page 1805
End Page 1814
Abstract
The waveform effect on dynamic bias temperature instability (BTI) is systematically studied for both p- and nMOSFETs with ultrathin SiON gate dielectrics by using a modified direct-current current-voltage method to monitor the stress-induced interface trap density. Interface traps are generated at the inversion gate bias (negative for pMOSFETs and positive for nMOSFETs) and are partially recovered at the zero or accumulation gate bias. Devices under high-frequency bipolar stress exhibit a significant frequency-dependent degradation enhancement. Approximate analytical expressions of the interface trap generation for devices under the static, unipolar, or bipolar stress are derived in the framework of conventional reaction-diffusion (R-D) model and with an assumption that additional interface traps (N*it) are generated in each cycle of the dynamic stress. The additional interface trap generation is proposed to originate from the transient trapped carriers in the states at and/or near the SiO2/Si interface upon the gate voltage reversal from the accumulation bias to the inversion bias quickly, which may accelerate dissociation of Si-H bonds at the beginning of the stressing phase in each cycle. Hence, N*it depends on the interface-state density, the voltage at the relaxation (i.e., accumulation) bias, and the transition time of the stress waveform (the fall time for pMOSFETs and the rise time for nMOSFETs). The observed dynamic BTI behaviors can be perfectly explained by this modified R-D model.
Keywords
Bias temperature instability (BTI)
Direct-current current-voltage (DCIV)
Dynamic stress
Interface states
Interface trap generation
MOSFET
Reaction-diffusion (R-D) model
Reliability
NDC
Electrical engineering [ 540 ]
Language
eng
Resource Type journal article
Publisher
IEEE
Date of Issued 2006-08
Rights
Copyright (c) 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Publish Type Version of Record
Access Rights open access
Source Identifier
[ISSN] 0018-9383
[DOI] 10.1109/TED.2006.877876
[NCID] AA00667820
[DOI] http://dx.doi.org/10.1109/TED.2006.877876