Enhancement of BTI degradation in pMOSFETs under high-frequency bipolar gate bias

Zhu Shiyang

Nakajima Anri

Ohashi Takuo

Miyake Hideharu

IEEE Electron Device Letters

Negative bias temperature (NBT) instability of p-MOSFETs with ultrathin SiON gate dielectric has been investigated under various gate bias configurations. The NBT-induced interface trap density (ΔNit) under unipolar bias is essentially lower than that under static bias, and is almost independent of the stress frequency up to 10 MHz. On the contrary, ΔNit under bipolar pulsed bias of frequency larger than about 10 kHz is significantly enhanced and exhibits a strong frequency dependence, which has faster generation rate and smaller activation energy as compared to other stress configurations. The degradation enhancement is attributed to the energy to be contributed by the recombination of trapped electrons and free holes upon the silicon surface potential reversal from accumulation to inversion.

Dynamic stress

Negative bias temperature instability (NBTI)

pMOSFETs

Recombination

Ultrathin gate oxide

電気工学 [ 540 ]

英語

Copyright (c) 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

[ISSN] 0741-3106

[DOI] 10.1109/LED.2005.848075

[NCID] AA00231428

[DOI] http://dx.doi.org/10.1109/LED.2005.848075