Fabrication of Si single-electron transistors having double SiO2 barriers
Applied Physics Letters Volume 80 Issue 24
Page 4617-4619
published_at 2002-06-17
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| File | |
| Title ( eng ) |
Fabrication of Si single-electron transistors having double SiO2 barriers
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| Creator |
Ito Yuhei
Hatano Tsuyoshi
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| Source Title |
Applied Physics Letters
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| Volume | 80 |
| Issue | 24 |
| Start Page | 4617 |
| End Page | 4619 |
| Abstract |
We fabricated Si single-electron transistors (SETs) having double SiO2 barriers and a polycrystalline Si (poly-Si) dot. The fabrication method of this device is completely compatible with the complementary metal–oxide–semiconductor technology, and the position of the poly-Si dot is self-aligned between the source and drain regions. The device exhibits drain current (Id) oscillation against gate voltage. From the dot size dependence of the electrical characteristics, the Id oscillation is considered to be due to the Coulomb blockade effect caused by poly-Si grains in the poly-Si dot. The self-alignment of the poly-Si dot in the fabrication process also means that the SET is promising for practical use.
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| Language |
eng
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| Resource Type | journal article |
| Publisher |
American Institute of Physics
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| Date of Issued | 2002-06-17 |
| Rights |
Copyright (c) 2002 American Institute of Physics.
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| Publish Type | Version of Record |
| Access Rights | open access |
| Source Identifier |
[ISSN] 0003-6951
[DOI] 10.1063/1.1485306
[NCID] AA00543431
[DOI] http://dx.doi.org/10.1063/1.1485306
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