A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones

Mondal Md Nazrul Islam

Nakano Koji

Ito Yasuaki

IEICE Transactions on Information and Systems

Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. However, most of FPGAs support synchronous read operations, but do not support asynchronous read operations. The main contribution of this paper is to provide one of the potent approaches to resolve this problem. We assume that a circuit using asynchronous ROMs designed by a non-expert or quickly designed by an expert is given. Our goal is to convert this circuit with asynchronous ROMs into an equivalent circuit with synchronous ones. The resulting circuit with synchronous ROMs can be embedded into FPGAs. We also discuss several techniques to decrease the latency and increase the clock frequency of the resulting circuits.

FPGA

block RAMs

asynchronous read operations

rewriting algorithm

Information science [ 007 ]

eng

電子情報通信学会

Copyright (c) 2011 The Institute of Electronics, Information and Communication Engineers

[ISSN] 0916-8532

[DOI] 10.1587/transinf.E94.D.2378

[NCID] AA10826272

[DOI] http://dx.doi.org/10.1587/transinf.E94.D.2378