A Study on Timing-Driven Placement and Routing Algorithms in VLSI Layout Design

VLSIレイアウト設計におけるタイミングドリブン配置・配線アルゴリズムに関する研究

Koide Tetsushi

Advancements in semi-conductor technology has made it possible for VLSI circuits to contain even millions of gates. In addition, we expect VLSI circuits to realize better and wider performance, resulting in requiring faster operational speed and higher clock frequency. This, in turn, makes interconnection delays in wiring appear as another major factor that cannot be neglected in evaluating the performance of a chip. Therefore layout design can no longer disregard interconnection delays against gate delays, and there is an urgency to develop timing-driven layout tools which do explicitly take interconnection delays into account.

The main goal of this dissertation is to propose the timing-driven placement and global routing algorithms for two typical layout styles available to us: the one is the standard cell layout style mainly used for designing ASICs, and the other is the building block layout style used for designing microprocessors etc.. The proposed algorithms avoid violation of timing requiremerits of a VLSI circuit so as to prevent decline in the performance of the circuit. They also minimize the chip area and the total wire length by estimating the routing area during placement and global routing. Consequently, the proposed algorithms can produce layout design of a VLSI circuit, without any violation of the timing requirement, in short turn-around-time.

Chapter 1 gives a general introduction to the VLSI layout design and the timing-driven layout problem, and addresses the objectives of this dissertation. The timing-driven layout design for the standard cell layout is discussed in Chapter 2 to Chapter 4, and that for the building block layout in Chapter 5.

In Chapter 2, the placement problem for the standard cell layout is discussed and a pathbased timing-driven placement algorithm is proposed based on hierarchical partitioning and nonlinear programming with the Elmore delay model. Moreover, to reduce the computation time further, the proposed placement algorithm is extended to a parallel algorithm running on a multi-processor workstation with shared memory. Its effectiveness is shown through numerical experiments.

The global routing problem for the standard cell layout is examined in Chapter 3; a pathbased timing-driven global routing algorithm is proposed considering the channel density minimization with Elmore delay. In order to effectively utilize the over-the-cell area, the proposed algorithm is extended to take the over-the-cell routing into account. Experimental results are also shown to demonstrate the effectiveness of the proposed algorithm.

In Chapter 4, the detailed routing problem for the standard cell layout that makes use of the over-the-cell area is treated, referred to as over-the-cell channel routing. Since the conventional standard cell models were originally developed not for over-the-cell channel routing but rather for conventional channel routing, they are not always suitable for the former. Thus, new standard cell models are proposed, which are suitable for the over-the-cell routing, and new over-the-cell channel routing algorithms are devised for the proposed cell models. Simulations have demonstrated the effectiveness of the proposed routers. The proposed algorithms can be also applied to conventional as well as the proposed cell models and can produce the comparable results for the conventional cell models to the conventional routers.

Chapter 5 deals with several layout problems for the building block layout, such as floorplanning, pin assignment, and global routing. In the building block layout, there are two types of blocks, that is, hard blocks and soft blocks. For the former, they are pre-designed and the shapes and pin positions of the blocks are pre-determined. On the other hand, since they are not pre-designed in the latter, it is needed to specify the exact shapes and pin positions in the layout design. Thus, a timing-driven floorplanning algorithm is newly proposed to determine the shapes of soft blocks as well as the positions of blocks so as to minimize the chip area. For pin assignment and global routing, as opposed to conventional approaches, pin assignment and global routing problems are combined into one problem so as to reduce the chip area, and a timing-driven algorithm integrating global routing and coarse pin assignment is proposed. The proposed algorithm can also determine the shape and the position of soft blocks. Finally, channel pin assignment is discussed and an optimal algorithm is proposed for the channel pin assignment problem, which minimizes both the channel density and total wire length. Experimental results for the industrial circuits show that the proposed algorithms are efficient and effective.

Finally, Chapter 6 summarizes the results of this dissertation and discusses topics related to future research.

Electrical engineering [ 540 ]

eng

Copyright(c) by Author

広島大学