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ID 33775
本文ファイル
著者
Mondal, Md Nazrul Islam
Ito, Yasuaki
キーワード
FPGA
block RAMs
asynchronous read operations
rewriting algorithm
NDC
情報科学
抄録(英)
Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. However, most of FPGAs support synchronous read operations, but do not support asynchronous read operations. The main contribution of this paper is to provide one of the potent approaches to resolve this problem. We assume that a circuit using asynchronous ROMs designed by a non-expert or quickly designed by an expert is given. Our goal is to convert this circuit with asynchronous ROMs into an equivalent circuit with synchronous ones. The resulting circuit with synchronous ROMs can be embedded into FPGAs. We also discuss several techniques to decrease the latency and increase the clock frequency of the resulting circuits.
掲載誌名
IEICE Transactions on Information and Systems
E94D巻
12号
開始ページ
2378
終了ページ
2388
出版年月日
2011-12
出版者
電子情報通信学会
ISSN
0916-8532
NCID
出版者DOI
言語
英語
NII資源タイプ
学術雑誌論文
広大資料タイプ
学術雑誌論文
DCMIタイプ
text
フォーマット
application/pdf
著者版フラグ
publisher
権利情報
Copyright (c) 2011 The Institute of Electronics, Information and Communication Engineers
関連情報URL
部局名
工学研究科