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ID 21040
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別タイトル
AN ARCHITECTURAL STUDY ON MASSIVE MULTIPROCESSOR SYSTENS
著者
NDC
電気工学
抄録(英)
The computer architecture has been explored for higher performance, higher facilitate and/or more reliable systems at lower costs ( sometimes at any cost ). Parallel processing with multiprocessors has been employed by many researchers as a suitable technology for the improvements, and has been realized in experimental or commercial machines consisting of up to 10<2> processors. In particular, a lot of proposals for new supercomputer architectures aimed at increasing machine performance by an order of magnitude have come out in the past several years. Decreasing costs and increasing density of CPU and memory chips due to the recent advanced VLSI technology have made such computer architectures feasible even if it is a Massive Multxprocessor system ( in short, MMS ) con figuring more than 10<3> processing elements. However, there remain a lot of problems to be solved toward realization of the MMS's efficiently performing a job.

The goal of this dissertation is to provide a design methodology of such MMS-s based on the architecture aimed at increasing their performance. Though several levels of the architectures are investigated, we mainly focus on the PMS ( Processor-Memory- Swxtch ) level because ,systems based on the architecture allow the design flexibility of their parallelism, and have great possibility of a realization at high cost-performance.

On the basis of several experiments using multiprocessor UNIP with 32 processors, the dissertation describes a massive multiprocessor simulator for performance evaluation and interconnection networks for MMS-s based on a new device technology, i.e., 3-dimensional integrated circuits.

First, Chapter 1 surveys studies on computer architectures toward higher performance of computing systems in various levels.

In Chapter 2, multiprocessor approaches are presented. Basic parallel processing schemes and typical multiprocessor configurations are summarized, and then, a fabrication of experimental multiprocessor system UNIP is described. After several experiments using UNIP are demonstrated, essential and crucial issues of multiprocessors derived from that experience are summarized.

In Chapter 3, a modeling of MMS programs for performance evaluation using the parallel programming scheme is proposed. The model which is largely intuitive, is applicable to a simulater for the performance evaluation of MMS s in which the interprocessor communication cost can be measured. After a description language of the programming scheme is described, the simulator implemented on the UNIX system and simulatxon analysis on the experimental results are demonstrated.

In Chapter 4. a new type of common memory ( in short, 3-D CM ) based on a technology of 3-dimensional integrated circuits is proposed and its fundamental properties are described. communication module for connecting processors using 3-D CM and processor interconnect!on networks for MMS's, consisting of the modules are demonstrated. A brief analysis of the network performance is also described.

Finally, in Chapter 5, we discuss and summarize further problems to realize high-performance MMS's.
言語
英語
NII資源タイプ
学位論文
広大資料タイプ
学位論文
DCMIタイプ
text
フォーマット
application/pdf
権利情報
Copyright(c) by Author
関連情報URL(references)
http://ir.lib.hiroshima-u.ac.jp/00020809
http://ir.lib.hiroshima-u.ac.jp/00020810
学位記番号
甲第591号
授与大学
広島大学(Hiroshima University)
学位名
博士(工学)
学位名の英名
Engineering
学位の種類の英名
doctoral
学位授与年月日
1986-03-25
部局名
情報メディア教育研究センター