Negative bias temperature (NBT) instability of p-MOSFETs with ultrathin SiON gate dielectric has been investigated under various gate bias configurations. The NBT-induced interface trap density (ΔNit) under unipolar bias is essentially lower than that under static bias, and is almost independent of the stress frequency up to 10 MHz. On the contrary, ΔNit under bipolar pulsed bias of frequency larger than about 10 kHz is significantly enhanced and exhibits a strong frequency dependence, which has faster generation rate and smaller activation energy as compared to other stress configurations. The degradation enhancement is attributed to the energy to be contributed by the recombination of trapped electrons and free holes upon the silicon surface potential reversal from accumulation to inversion.