Fabrication of Si single-electron transistors having double SiO2 barriers
この文献の参照には次のURLをご利用ください : https://ir.lib.hiroshima-u.ac.jp/00018590
ID | 18590 |
本文ファイル | |
著者 |
Ito, Yuhei
Hatano, Tsuyoshi
|
抄録(英) | We fabricated Si single-electron transistors (SETs) having double SiO2 barriers and a polycrystalline Si (poly-Si) dot. The fabrication method of this device is completely compatible with the complementary metal–oxide–semiconductor technology, and the position of the poly-Si dot is self-aligned between the source and drain regions. The device exhibits drain current (Id) oscillation against gate voltage. From the dot size dependence of the electrical characteristics, the Id oscillation is considered to be due to the Coulomb blockade effect caused by poly-Si grains in the poly-Si dot. The self-alignment of the poly-Si dot in the fabrication process also means that the SET is promising for practical use.
|
掲載誌名 |
Applied Physics Letters
|
巻 | 80巻
|
号 | 24号
|
開始ページ | 4617
|
終了ページ | 4619
|
出版年月日 | 2002-06-17
|
出版者 | American Institute of Physics
|
ISSN | 0003-6951
|
NCID | |
出版者DOI | |
言語 |
英語
|
NII資源タイプ |
学術雑誌論文
|
広大資料タイプ |
学術雑誌論文
|
DCMIタイプ | text
|
フォーマット | application/pdf
|
著者版フラグ | publisher
|
権利情報 | Copyright (c) 2002 American Institute of Physics.
|
関連情報URL | |
部局名 |
ナノデバイス・システム研究センター
|