Development of High-Speed Silicon Devices and Their Design with Advanced Physical Models
Use this link to cite this item : https://ir.lib.hiroshima-u.ac.jp/00036789
diss_otsu3169.pdf 18.9 MB
In the field of high-speed silicon devices, silicon bipolar junction transistors (BJTs) had played a major role from the 1970s to the end of the 1980s. However, in the 1990s complementary metal-oxide-semiconductor (CMOS) .field effect transistors (FETs) have been replacing their position. This dissertation explains the reasons why BJTs were suitable for high-speed operation. This is concluded from the development of technologies for BJTs and the analyses of devices fabricated with these technologies. At the same time it clarifies why they were replaced by CMOS transistors. The BJT's high driving capability and large power dissipation were the both sides of a sword.
In the case of high-speed CMOS devices, the driving current of MOSFET should be large enough, and device design must be based on precise comprehension of carrier transport in MOSFETs. Therefore, we need accurate device model as well as rigid device-structure information obtained by experiments. This dissertation describes the device design methodology not only based on inverse modeling to extract device structures consistent with all kinds of experimental results but also based on simulations by generalized hydrodynamic model and full-band Monte Carlo model. The background and concept of the methodology is also discussed, and its necessity in future development is clarified. Moreover, hot carrier modeling is discussed by employing full-band Monte Carlo device simulation. Also, this dissertation clarifies the fact there is no experimental evidence for the difference between the surface and bulk impact ionization mechanism in silicon. The reported difference in the literature was only caused by an unsound application of the local field model and was just an artifact.
Finally, by using these sophisticated models, the saturation drain current as well as hot carrier effects of subquarter micron MOSFETs are analyzed. MOSFET design strategy for the 0.1 μ m regime is discussed and the importance of shallow junction for source/drain extension is also clarified.
Thesis or Dissertation
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