Atomic-layer-deposited silicon-nitride/SiO2 stacked gate dielectrics for highly reliable p-metal–oxide–semiconductor field-effect transistors
Use this link to cite this item : https://ir.lib.hiroshima-u.ac.jp/00018596
ID | 18596 |
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creator |
Yoshimoto, Takashi
Kidera, Toshiro
Obata, Katsunori
Sunami, Hideo
Hirose, Masataka
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abstract | An extremely thin (~0.4 nm) silicon-nitride layer has been deposited on thermally grown SiO2 by an atomic-layer-deposition (ALD) technique. The boron penetration through the stacked gate dielectrics has dramatically been suppressed, and the reliability has been significantly improved, as confirmed by capacitance–voltage, gate-current–gate-voltage, and time-dependent dielectricbreakdown characteristics. The ALD technique allows us to fabricate an extremely thin, very uniform silicon-nitride layer with atomic-scale control.
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journal title |
Applied Physics Letters
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volume | Volume 77
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issue | Issue 18
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start page | 2855
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end page | 2857
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date of issued | 2000-10-30
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publisher | American Institute of Physics
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issn | 0003-6951
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ncid | |
publisher doi | |
language |
eng
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nii type |
Journal Article
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HU type |
Journal Articles
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DCMI type | text
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format | application/pdf
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text version | publisher
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rights | Copyright (c) 2000 American Institute of Physics.
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relation url | |
department |
Research Center for Nanodevices and Systems
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