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ID 18587
file
creator
Khosru, Quazi Deen Mohd
Yoshimoto, Takashi
abstract
We report a high-quality, ultrathin atomic-layer-deposited silicon–nitride/SiO2 stack gate dielectric. p+-polycrystalline silicon gate metal–oxide–semiconductor (MOS) capacitors with the proposed dielectrics showed enhanced reliability with respect to conventional SiO2. An exciting feature of suppressed soft-breakdown (SBD) events is observed in ramped voltage stressing which has been reconfirmed during time-dependent-dielectric breakdown measurements under constant field stressing. Introducing the idea of injected-carrier-induced localized physical damages resulting in the formation of conductive filaments near both Si/SiO2 and poly-Si/SiO2 interfaces, a model has been proposed to explain the SBD phenomena observed in the conventional SiO2 dielectrics. It is then consistently extended to explain the suppressed SBD in the proposed dielectrics. The reported dielectric can be a good choice to meet the urgent need for highly reliable ultrathin gate dielectrics in nanoscale complementary-MOS technology.
journal title
Applied Physics Letters
volume
Volume 79
issue
Issue 21
start page
3488
end page
3490
date of issued
2001-11-19
publisher
American Institute of Physics
issn
0003-6951
ncid
publisher doi
language
eng
nii type
Journal Article
HU type
Journal Articles
DCMI type
text
format
application/pdf
text version
publisher
rights
Copyright (c) 2001 American Institute of Physics.
relation url
department
Research Center for Nanodevices and Systems