Enhancement of BTI degradation in pMOSFETs under high-frequency bipolar gate bias
Use this link to cite this item : https://ir.lib.hiroshima-u.ac.jp/00015051
ID | 15051 |
file | |
creator |
Zhu, Shiyang
Ohashi, Takuo
Miyake, Hideharu
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subject | Dynamic stress
Negative bias temperature instability (NBTI)
pMOSFETs
Recombination
Ultrathin gate oxide
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NDC |
Electrical engineering
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abstract | Negative bias temperature (NBT) instability of p-MOSFETs with ultrathin SiON gate dielectric has been investigated under various gate bias configurations. The NBT-induced interface trap density (ΔNit) under unipolar bias is essentially lower than that under static bias, and is almost independent of the stress frequency up to 10 MHz. On the contrary, ΔNit under bipolar pulsed bias of frequency larger than about 10 kHz is significantly enhanced and exhibits a strong frequency dependence, which has faster generation rate and smaller activation energy as compared to other stress configurations. The degradation enhancement is attributed to the energy to be contributed by the recombination of trapped electrons and free holes upon the silicon surface potential reversal from accumulation to inversion.
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journal title |
IEEE Electron Device Letters
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volume | Volume 26
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issue | Issue 6
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start page | 387
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end page | 389
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date of issued | 2005-06
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issn | 0741-3106
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ncid | |
publisher doi | |
language |
eng
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nii type |
Journal Article
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HU type |
Journal Articles
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DCMI type | text
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format | application/pdf
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text version | publisher
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rights | Copyright (c) 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
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relation url | |
department |
Research Center for Nanodevices and Systems
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