Fabrication of Si single-electron transistors having double SiO2 barriers
Use this link to cite this item : https://ir.lib.hiroshima-u.ac.jp/00018590
ID | 18590 |
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creator |
Ito, Yuhei
Hatano, Tsuyoshi
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abstract | We fabricated Si single-electron transistors (SETs) having double SiO2 barriers and a polycrystalline Si (poly-Si) dot. The fabrication method of this device is completely compatible with the complementary metal–oxide–semiconductor technology, and the position of the poly-Si dot is self-aligned between the source and drain regions. The device exhibits drain current (Id) oscillation against gate voltage. From the dot size dependence of the electrical characteristics, the Id oscillation is considered to be due to the Coulomb blockade effect caused by poly-Si grains in the poly-Si dot. The self-alignment of the poly-Si dot in the fabrication process also means that the SET is promising for practical use.
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journal title |
Applied Physics Letters
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volume | Volume 80
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issue | Issue 24
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start page | 4617
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end page | 4619
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date of issued | 2002-06-17
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publisher | American Institute of Physics
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issn | 0003-6951
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ncid | |
publisher doi | |
language |
eng
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nii type |
Journal Article
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HU type |
Journal Articles
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DCMI type | text
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format | application/pdf
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text version | publisher
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rights | Copyright (c) 2002 American Institute of Physics.
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relation url | |
department |
Research Center for Nanodevices and Systems
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