NH3-annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability
Use this link to cite this item : https://ir.lib.hiroshima-u.ac.jp/00018588
ID | 18588 |
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creator |
Khosru, Quazi Deen Mohd
Yoshimoto, Takashi
Kidera, Toshirou
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abstract | Extremely thin (equivalent oxide thickness, Teq = 1.2 nm) silicon-nitride high-k (er = 7.2) gate dielectrics have been formed at low temperatures (<550 °C) by an atomic-layer-deposition (ALD) technique with subsequent NH3 annealing at 550 °C. A remarkable reduction in leakage current, especially in the low dielectric voltage region, which will be the operating voltage for future technologies, has made it a highly potential gate dielectric for future ultralarge-scale integrated devices. Suppressed soft breakdown events are observed in ramped voltage stressing. This suppression is thought to be due to a strengthened structure of Si–N bonds and the smoothness and uniformity at the poly-Si/ALD-silicon-nitride interface.
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journal title |
Applied Physics Letters
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volume | Volume 80
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issue | Issue 7
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start page | 1252
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end page | 1254
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date of issued | 2002-02-18
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publisher | American Institute of Physics
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issn | 0003-6951
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ncid | |
publisher doi | |
language |
eng
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nii type |
Journal Article
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HU type |
Journal Articles
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DCMI type | text
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format | application/pdf
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text version | publisher
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rights | Copyright (c) 2002 American Institute of Physics.
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relation url | |
department |
Research Center for Nanodevices and Systems
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