Interface trap and oxide charge generation under negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with ultrathin plasma-nitrided SiON gate dielectrics
Use this link to cite this item : https://ir.lib.hiroshima-u.ac.jp/00018600
ID | 18600 |
file | |
creator |
Zhu, Shiyang
Ohashi, Takuo
Miyake, Hideharu
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abstract | The interface trap generation (Δ Nit) and fixed oxide charge buildup (Δ Not) under negative bias temperature instability (NBTI) of p -channel metal-oxide-semiconductor field-effect transistors (p MOSFETs) with ultrathin (2 nm) plasma-nitrided SiON gate dielectrics were studied using a modified direct-current-current-voltage method and a conventional subthreshold characteristic measurement. Different stress time dependences were shown for Δ Nit and Δ Not. At the earlier stress times, Δ Nit dominates the threshold voltage shift (Δ Vth) and Δ Not is negligible. With increasing stress time, the rate of increase of Δ Nit decreases continuously, showing a saturating trend for longer stress times, while Δ Not still has a power-law dependence on stress time so that the relative contribution of Δ Not increases. The thermal activation energy of Δ Nit and the NBTI lifetime of p MOSFETs, compared at a given stress voltage, are independent of the peak nitrogen concentration of the SiON film. This indicates that plasma nitridation is a more reliable method for incorporating nitrogen in the gate oxide.
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journal title |
Journal of Applied Physics
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volume | Volume 98
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issue | Issue 11
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date of issued | 2005-12-01
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publisher | American Institute of Physics
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issn | 0021-8979
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ncid | |
publisher doi | |
language |
eng
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nii type |
Journal Article
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HU type |
Journal Articles
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DCMI type | text
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format | application/pdf
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text version | publisher
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rights | Copyright (c) 2005 American Institute of Physics.
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relation url | |
department |
Research Center for Nanodevices and Systems
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