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ID 15050
本文ファイル
著者
Ohashi, Takuo
Zhu, Shiyang
Yokoyama, Shigeyuki
Michimata, Shigetomi
Miyake, Hideharu
キーワード
Atomic layer deposition (ALD)
DRAM
MOSFET
Si nitride
Stack gate dielectrics
NDC
電気工学
抄録(英)
Atomic layer-deposited (ALD) Si-nitride/SiO"2 stack gate dielectrics were applied to high-performance transistors for future scaled DRAMs. The stack gate dielectrics of the peripheral pMOS transistors excellently suppress boron penetration. ALD stack gate dielectrics exhibit only slightly worse negative-bias temperature instability (NBTI) characteristics than pure gate oxide. Enhanced reliability in NBTI was achieved compared with that of plasma-nitrided gate SiO"2. Memory-cell (MC) nMOS transistors with ALD stack gate dielectrics show slightly smaller junction leakage than those with plasma-nitrided gate SiO"2 in a high-drain-voltage region, and have identical junction leakage characteristics to transistors with pure gate oxide. MCs having transistors with ALD stack gate dielectrics and those with pure gate oxide have the identical retention-time distribution. Taking the identical hole mobility for the transistors with ALD stack gate dielectrics to that for the transistors with pure gate oxide both before and after hot carrier injection (previously reported) into account, the ALD stack dielectrics are a promising candidate for the gate dielectrics of future high-speed, reliable DRAMs.
掲載誌名
IEEE Electron Device Letters
26巻
8号
開始ページ
538
終了ページ
540
出版年月日
2005-08
出版者
IEEE
ISSN
0741-3106
NCID
出版者DOI
言語
英語
NII資源タイプ
学術雑誌論文
広大資料タイプ
学術雑誌論文
DCMIタイプ
text
フォーマット
application/pdf
著者版フラグ
publisher
権利情報
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関連情報URL
部局名
ナノデバイス・システム研究センター