このエントリーをはてなブックマークに追加
ID 18587
本文ファイル
著者
Khosru, Quazi Deen Mohd
Yoshimoto, Takashi
抄録(英)
We report a high-quality, ultrathin atomic-layer-deposited silicon–nitride/SiO2 stack gate dielectric. p+-polycrystalline silicon gate metal–oxide–semiconductor (MOS) capacitors with the proposed dielectrics showed enhanced reliability with respect to conventional SiO2. An exciting feature of suppressed soft-breakdown (SBD) events is observed in ramped voltage stressing which has been reconfirmed during time-dependent-dielectric breakdown measurements under constant field stressing. Introducing the idea of injected-carrier-induced localized physical damages resulting in the formation of conductive filaments near both Si/SiO2 and poly-Si/SiO2 interfaces, a model has been proposed to explain the SBD phenomena observed in the conventional SiO2 dielectrics. It is then consistently extended to explain the suppressed SBD in the proposed dielectrics. The reported dielectric can be a good choice to meet the urgent need for highly reliable ultrathin gate dielectrics in nanoscale complementary-MOS technology.
掲載誌名
Applied Physics Letters
79巻
21号
開始ページ
3488
終了ページ
3490
出版年月日
2001-11-19
出版者
American Institute of Physics
ISSN
0003-6951
NCID
出版者DOI
言語
英語
NII資源タイプ
学術雑誌論文
広大資料タイプ
学術雑誌論文
DCMIタイプ
text
フォーマット
application/pdf
著者版フラグ
publisher
権利情報
Copyright (c) 2001 American Institute of Physics.
関連情報URL
部局名
ナノデバイス・システム研究センター