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ID 18588
file
creator
Khosru, Quazi Deen Mohd
Yoshimoto, Takashi
Kidera, Toshirou
abstract
Extremely thin (equivalent oxide thickness, Teq = 1.2 nm) silicon-nitride high-k (er = 7.2) gate dielectrics have been formed at low temperatures (<550 °C) by an atomic-layer-deposition (ALD) technique with subsequent NH3 annealing at 550 °C. A remarkable reduction in leakage current, especially in the low dielectric voltage region, which will be the operating voltage for future technologies, has made it a highly potential gate dielectric for future ultralarge-scale integrated devices. Suppressed soft breakdown events are observed in ramped voltage stressing. This suppression is thought to be due to a strengthened structure of Si–N bonds and the smoothness and uniformity at the poly-Si/ALD-silicon-nitride interface.
journal title
Applied Physics Letters
volume
Volume 80
issue
Issue 7
start page
1252
end page
1254
date of issued
2002-02-18
publisher
American Institute of Physics
issn
0003-6951
ncid
publisher doi
language
eng
nii type
Journal Article
HU type
Journal Articles
DCMI type
text
format
application/pdf
text version
publisher
rights
Copyright (c) 2002 American Institute of Physics.
relation url
department
Research Center for Nanodevices and Systems